1. Technical Field
The present invention relates to a phase-change memory device. More particularly, the present invention relates to a write driver circuit in a phase change memory device and a method for applying a write current.
2. Discussion of the Related Art
Random Access Memory (RAM) is commonly used to store data in electronic systems, such as a computer system, communication equipment, digital cameras, and other electronic devices.
A non-volatile RAM memory cell may include a phase change material. Phase change memory devices use phase change materials, i.e., materials that can be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application. Typical phase change materials suitable for such application include those utilizing various chalcogenide elements. Chalcogenide phase change memory operates by switching between a high resistance amorphous state and a low resistance crystalline state by heating the chalcogenide storage medium.
As used herein, the term Phase change memory (PC-RAM or PRAM), are any RAMs that store data using a conductive/resistive element having two states with different resistances, and includes Chalcogenide RAM (C-RAM), Ovonic Unified Memory (OUM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Resistance RAM (RRAM) and also includes those RAMs with metal dissolved in chalcogenide glass which form a metal short across the chalcogenide for the low resistance state, called the programmable metallization chalcogenide RAMs (PMC-RAM or PMCm). The Resistance RAM or RRAM uses a phase change metal oxide or PCMO in place of the chalcogenide. Also a Polymer Resistance memory uses current to create a reversible conductive path through a polymer.
Data can be stored in a phase change memory (PC-RAM) cell composed of the phase change material by changing the phase of the material to one of two detectable physical states. For example, a first physical state of the phase change material may include a high resistance state, and a second physical state-of the material may include a low resistance state. If the high resistance state indicates a binary “1,” the low resistance state indicates a binary “0”. Phase change memory (PC-RAM) are generally “non-volatile” in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reset.
A phase change memory device typically includes a memory cell array having a plurality of phase change memory cells and may be employed in the electronic system as a substitute for a volatile RAM device such as DRAM.
FIG. 1 is a circuit block diagram of a portable electronic system illustrating an example of the use of a conventional phase change memory (PC-RAM) device 10. A phase change memory device 10, operatively connected to a microprocessor 4 through a bus line L3, functions as a main memory of the portable electronic system. A battery 2 supplies electrical power to the microprocessor 4, to an I/O (Input/Output) circuit 6, and to the phase change memory device 10 through a power supply line L4. If received data is provided to the I/O 6 through the line L1, the microprocessor 4 receives and processes the received data through a line L2, and then applies the received data or processed data to the phase change memory device 10 through the bus line L3. The phase change memory device 10 stores the (received or processed ) data in its phase change memory cells. Further, the data stored in the memory cells of the phase change memory device 10 may be read by the microprocessor 4 and may be outputted to exterior circuits through line L2, the I/O circuit 6, and line L2.
Even when electrical power from the battery 2 is not supplied to the power supply line L4, (nor to the phase change memory device 10) the data stored in the memory cells of the phase change memory device 10 is not lost, due to the non-volatile storage properties of the phase change material. Thus, the phase change memory device 10 is a non-volatile memory device, and is different from a DRAM in this respect. Furthermore, the phase change memory device 10 also has high-speed operation and low power consumption properties.
FIG. 2 is a schematic circuit and block diagram of the phase change memory device 10 shown in FIG. 1. Referring to FIG. 2, the functional blocks of the phase change memory device 10 are the same as in a typical DRAM except for the phase change memory cells (e.g., cell 52).The phase change memory device 10 includes an address buffer and signal generation circuit 20, a row decoder 30, a column path and column decoder 40, a write driver circuit 100, a read amplification circuit 60, and a data functional blocks are somewhat different from those of corresponding blocks of the DRAM because of special read and write operation properties of the phase change memory cells (e.g., cell 52).
In FIG. 2, a unit memory cell 52, the basic unit of a memory cell array and sense amplifier 50 is composed of: an access transistor NT and a variable resistor GST. The variable resistor GST corresponds to the phase change material. A gate of the access transistor NT is connected to a word line WL forming a row of the memory cell array., The variable resistor GST is connected between a bit line BL and the access transistor NT. The bit line BL defines a column of the memory cell array.
FIG. 3 is a state diagram showing state changes for the phase change material in the phase change memory cell 52 in FIG. 2. The phase change material, which functions as the variable resistor GST, experiences state changes as shown in FIG. 3. Referring to FIG. 3, there is shown a phase change material film 55 sandwiched between an upper electrode 56 and a lower electrode 54. The phase change material film 55 may be composed of a phase change material, for example, GexSbyTe2, the resistivity (resistance) of which is changed when its phase becomes crystalline or amorphous, which is determined based upon temperature and heating time.
FIG. 4 shows phase change properties of the phase change material shown in FIG. 3 relative to time and temperature. Referring to FIG. 4, the horizontal axis indicates time, and the vertical axis indicates temperature T. As denoted in the graph by reference numbers 12, 10 and 14, an amorphous state of the phase change material GST may be achieved by heating the temperature of phase change material GST above a melting temperature Tm and then immediately cooling it. Further, as denoted by reference numbers 22, 20 and 24, the crystalline state may be achieved by heating the temperature of phase change material GST above the crystallization temperature Tx for a predetermined time and then cooling it. As denoted by reference numerals ST1 and ST2 (in FIG. 3), the change of the state of the phase change material GST from an amorphous state to a crystalline state is defined as “SET”; and the change of the state of the phase change material GST from the crystalline state to the amorphous state is defined as RESET. Resistance of the phase change material GST in the amorphous state is significantly higher than that of its resistance in the crystalline state.
Known methods for heating the phase change material film 55 shown in FIG. 3 includes a method using a laser beam, a method using a current, and the like. The method using a current is preferred in a memory chip embodiment. When the method using a current is applied, the phase change material film 55 changes between a SET or RESET state due to joule heating generated, which is determined by the magnitude and application time of electric current.
FIG. 5 is a diagram showing waveforms of respective current pulses applied for changing the phase change material GST shown in FIG. 3 into a first (amorphizing) or second (crystalline) state using joule heating. In FIG. 5, the horizontal axis indicates time, but the vertical axis indicates the magnitude of a current I through the phase change material GST. In FIG. 5, if current magnitudes for respective pulses (G1, G2) are compared to each other, it is seen that the magnitude of current of RESET pulse G1 is higher than that of SET pulse G2. If application times of current I are compared to each other, the application time of the SET pulse G2 is longer than that of the RESET pulse G1. The RESET pulse G1 and the SET pulse G2 of FIG. 5 represent write currents, which must be respectively applied to the memory cell to cause a binary “1” or “0” to be stored in the write operation mode.
Hereinafter, a write operation (or a program operation) to store data in the phase change memory cell 52, will be briefly described with reference to FIGS. 2 to 5 . And then a read operation of sensing stored data and outputting it to the exterior of the memory will be subsequently described.
Conventionally, write data WDATA Is to be stored in (written to) a phase change memory cell (e.g., 52) connected between a word line (e.g., WL1) and a bit line (e.g., BL1) in the memory cell array 50 of FIG. 2. The first word line WL1 is activated by an address decoding operation of the row decoder 30. Meanwhile, the first bit line BL1 is selected by a decoding operation of the column path and column decoder 40. The write data WDATA is applied to a write driver circuit 100 via the data input/output buffer 70. If the write data WDATA is logic “1”, the write driver circuit 100 applies the RESET pulse G1 (shown in FIG. 5) to a single data line SDL as a write current If the write data WDATA is logic “0”, the write driver circuit 100 applies the SET pulse G2 (shown in FIG. 5) to the single data line SDL as the write current. When the RESET pulse G1 is applied to the first bit line BL1, the phase change material film (55 in FIG. 3) of the selected phase change memory cell (e.g., 52) is heated at a temperature indicated in the AMORPHIZING RESET PULSE graph 10 of FIG. 4 and then is cooled, so that it is reset (as in the memory cell 52-1 of FIG. 3). As a result, the reset memory cell (e.g. 52) has a high resistance state, functioning as a memory cell that stores data “1”. On the other hand, when the SET pulse G1 Is applied to the first bit line BL1, the phase change material film 55 of the selected phase change memory cell (e.g., 52) is heated to a temperature indicated in the CRYSTALLIZING (SET) PULSE graph 20 of FIG. 4 and then is cooled, so that it Is set (as in the memory cell 52-2 of FIG. 3). As a result, the set memory cell (e.g., 52) has a relatively lower resistance state, functioning as a memory cell that stores data “0”.
Data stored in a memory cell (e.g., 52) as data “1” or “0” is read via the first bit line BL1 if the first bit line BL1 is selected. If data “1” has been stored, the level of cell pass-through current that flows from the bit line BL1 (to ground) is relatively lower since the memory cell (e.g. 52) is in a high resistance state. Otherwise, if data “0” has been stored, the level of cell pass-through current is relatively higher since the memory cell (e.g., 52) is in a low resistance state. Accordingly, whether the data stored in the memory cell (e.g. 52) is 1 or 0 can be determined by connecting and driving a current sense amplifier to each bit line. The sense amp senses the cell pass-through current. Alternatively, whether the data stored In the memory cell (e.g. 52) is 1 or 0 can be determined by connecting to the bit line a voltage sense amplifier, which senses a voltage caused by the cell pass-through current,. The data read as 1 or 0 is outputted to the data input/output buffer 70 via the column path and column decoder 40 and the read amplification circuit 60. The read amplification circuit 60 is a circuit that functions to re-amplify the data outputted from the bit line sense amplifiers.
One of the technologies for reading data from a phase change memory cell is disclosed in U.S. Pat. No. 6,608,773 to Lowrey et al. issued in Aug. 19, 2003.
One of the technologies of forming the phase change memory cell is disclosed in U.S. Pat. No. 6,605,821 to Heon Lee et al. issued in Aug. 12, 2003.
An example of technology for performing a write operation In the phase change memory device is disclosed in U.S. Pat. No. 6,545,907 to Lowrey et al. issued in Apr. 8, 2003. The U.S. Pat. No. 6,545,907 discloses a method for performing a write operation with reset and set pulses as write currents. However, there is a potential problem that a “current output shift” can occurs in a write current generation circuit, such as a write driver circuit or the like. Also there is no countermeasure for controlling the write current output in the case where a phase change memory cell having a phase change material has a “phase change property shift” caused by an external factor or a process change.
Thus, if the current output from the write current generation circuit, such as a write driver circuit or the like, is not generated as a predefined value, e.g., due to the external factor or process change, current levels of the reset pulse and the set pulse will not be generated as predefined values, thereby degrading the reliability of the write operation. Further, in the case where the phase change memory cell having the phase change material has a “phase change property shift”, e.g., due to an external factor or process change, it is difficult to guarantee the reliability of the write operation even though the current levels of the reset and set pulses are applied with the predefined value. If the reliability of the write operation is degraded, it will reduce manufacture yield in production of the phase change memory device.
Accordingly, there is a need for a technology allowing the write operation to be more precisely performed by controlling the write current output from the write driver circuit for each phase change memory cell array blocks or memory chips.